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| author | Ezra Sitorus <ezra.sitorus@arm.com> | 2023-12-07 15:41:05 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@arm.com> | 2023-12-07 17:16:21 +0000 |
| commit | 8e3ae874b21bdd8da32afefa6f6f60913481564c (patch) | |
| tree | acb99e656ccb1fb4210f4b9d64481f9e8e4c7a4f /gcc/tree-vect-loop.cc | |
| parent | 8fff3f065277f13176c320f22c4ed766a82c5d8e (diff) | |
| download | gcc-8e3ae874b21bdd8da32afefa6f6f60913481564c.zip gcc-8e3ae874b21bdd8da32afefa6f6f60913481564c.tar.gz gcc-8e3ae874b21bdd8da32afefa6f6f60913481564c.tar.bz2 | |
arm: vld1_types_x3 ACLE intrinsics
This patch is part of a series of patches implementing the _xN
variants of the vld1 intrinsic for the arm port. This patch adds the
_x3 variants of the vld1 intrinsic.
The previous vld1_x3 has been updated to vld1q_x3 to take into
account that it works with 4-word-length types. vld1_x3 is now
only for 2-word-length types.
ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/
ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/
gcc/ChangeLog:
* config/arm/arm_neon.h
(vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New
(vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
(vld1_f16_x3, vld1_f32_x3): New.
(vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
(vld1_bf16_x3): New.
(vld1q_types_x3): Updated to use vld1q_x3 from
arm_neon_builtins.def
* config/arm/arm_neon_builtins.def
(vld1_x3): Updated entries.
(vld1q_x3): New entries, but comes from the old vld1_x2
* config/arm/neon.md (neon_vld1q_x3<mode>): Updated from
neon_vld1_x3<mode>.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/vld1_base_xN_1.c: Add new tests.
* gcc.target/arm/simd/vld1_bf16_xN_1.c: Add new tests.
* gcc.target/arm/simd/vld1_fp16_xN_1.c: Add new tests.
* gcc.target/arm/simd/vld1_p64_xN_1.c: Add new tests.
Diffstat (limited to 'gcc/tree-vect-loop.cc')
0 files changed, 0 insertions, 0 deletions