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author | Pan Li <pan2.li@intel.com> | 2024-06-03 10:43:10 +0800 |
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committer | Pan Li <pan2.li@intel.com> | 2024-06-07 08:53:38 +0800 |
commit | 93f44e18cddb2b5eb3a00232d3be9a5bc8179f25 (patch) | |
tree | 96d08e6999d114ba814cfa72f02b48acb84e5032 /gcc/tree-vect-loop.cc | |
parent | a171aac72408837ed0b20e3912a22c5b4891ace4 (diff) | |
download | gcc-93f44e18cddb2b5eb3a00232d3be9a5bc8179f25.zip gcc-93f44e18cddb2b5eb3a00232d3be9a5bc8179f25.tar.gz gcc-93f44e18cddb2b5eb3a00232d3be9a5bc8179f25.tar.bz2 |
RISC-V: Add testcases for scalar unsigned SAT_ADD form 5
After the middle-end support the form 5 of unsigned SAT_ADD and
the RISC-V backend implement the scalar .SAT_ADD, add more test
case to cover the form 5 of unsigned .SAT_ADD.
Form 5:
#define SAT_ADD_U_5(T) \
T sat_add_u_5_##T(T x, T y) \
{ \
return (T)(x + y) < x ? -1 : (x + y); \
}
Passed the riscv fully regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test macro for form 5.
* gcc.target/riscv/sat_u_add-21.c: New test.
* gcc.target/riscv/sat_u_add-22.c: New test.
* gcc.target/riscv/sat_u_add-23.c: New test.
* gcc.target/riscv/sat_u_add-24.c: New test.
* gcc.target/riscv/sat_u_add-run-21.c: New test.
* gcc.target/riscv/sat_u_add-run-22.c: New test.
* gcc.target/riscv/sat_u_add-run-23.c: New test.
* gcc.target/riscv/sat_u_add-run-24.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc/tree-vect-loop.cc')
0 files changed, 0 insertions, 0 deletions