RISC-V: Implement .SAT_SUB for unsigned vector int

As the middle support of .SAT_SUB committed,  implement the unsigned
vector int of .SAT_SUB for the riscv backend.  Consider below example
code:

void __attribute__((noinline))                                       \
vec_sat_u_sub_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \
{                                                                    \
  unsigned i;                                                        \
  for (i = 0; i < limit; i++)                                        \
    {                                                                \
      T x = op_1[i];                                                 \
      T y = op_2[i];                                                 \
      out[i] = (x - y) & (-(T)(x >= y));                             \
    }                                                                \
}

Before this patch:
  ...
  vsetvli a5,a3,e64,m1,ta,mu
  slli    a4,a5,3
  vle64.v v2,0(a1)
  vle64.v v1,0(a2)
  vmsgeu.vv       v0,v2,v1
  vmv1r.v v3,v4
  vsub.vv v3,v2,v1,v0.t
  vse64.v v3,0(a0)
  ...

After this patch:
  ...
  vsetvli a5,a3,e64,m1,ta,ma
  slli    a4,a5,3
  vle64.v v1,0(a1)
  vle64.v v2,0(a2)
  vssubu.vv       v1,v1,v2
  vse64.v v1,0(a0)
  ...

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/ChangeLog:

	* config/riscv/autovec.md (ussub<mode>3): Add new pattern impl
	for the unsigned vector modes.
	* config/riscv/riscv-protos.h (expand_vec_ussub): Add new func
	decl to expand .SAT_SUB for vector mode.
	* config/riscv/riscv-v.cc (emit_vec_saddu): Add new func impl
	to expand .SAT_SUB for vector mode.
	(emit_vec_binary_alu): Add new helper func to emit binary alu.
	(expand_vec_ussub): Leverage above helper func.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add helper macros for test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-3.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-4.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions