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| author | Georg-Johann Lay <avr@gjlay.de> | 2024-02-15 13:53:34 +0100 |
|---|---|---|
| committer | Georg-Johann Lay <avr@gjlay.de> | 2024-02-15 14:07:53 +0100 |
| commit | 5cff288c2dae4ea709df067cf398f23e214b2e80 (patch) | |
| tree | 51bf4e11f2807d10e6376614b29f861f4582a0a4 /gcc/tree-vect-loop.cc | |
| parent | 84da9bca72558119974db307208eb2fa2b8ad5dd (diff) | |
| download | gcc-5cff288c2dae4ea709df067cf398f23e214b2e80.zip gcc-5cff288c2dae4ea709df067cf398f23e214b2e80.tar.gz gcc-5cff288c2dae4ea709df067cf398f23e214b2e80.tar.bz2 | |
AVR: target 113927 - Simple code triggers stack frame for Reduced Tiny.
The -mmcu=avrtiny cores have no ADIW and SBIW instructions. This was
implemented by clearing all regs out of regclass ADDW_REGS so that
constraint "w" never matched. This corrupted the subset relations of
the register classes as they appear in enum reg_class.
This patch keeps ADDW_REGS like for all other cores, i.e. it contains
R24...R31. Instead of tests like test_hard_reg_class (ADDW_REGS, *)
the code now uses avr_adiw_reg_p (*). And all insns with constraint "w"
get "isa" insn attribute value of "adiw".
Plus, a new built-in macro __AVR_HAVE_ADIW__ is provided, which is more
specific than __AVR_TINY__.
gcc/
PR target/113927
* config/avr/avr.h (AVR_HAVE_ADIW): New macro.
* config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
* config/avr/avr.cc (avr_adiw_reg_p): New function.
(avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
* config/avr/avr.md: Same.
(attr "isa") <tiny, no_tiny>: Remove.
<adiw, no_adiw>: Add.
(define_insn, define_insn_and_split): When an alternative has
constraint "w", then set attribute "isa" to "adiw".
* config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
Built-in define __AVR_HAVE_ADIW__.
* doc/invoke.texi (AVR Options): Document it.
Diffstat (limited to 'gcc/tree-vect-loop.cc')
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