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| author | Lulu Cheng <chenglulu@loongson.cn> | 2024-03-05 14:43:04 +0800 |
|---|---|---|
| committer | Lulu Cheng <chenglulu@loongson.cn> | 2024-03-09 09:46:23 +0800 |
| commit | 3a3fbec0a4d3f36de58df9ef0b3992a3ffb359c2 (patch) | |
| tree | 0d119e1b587eac4b3d7f0ae1e9c26245841b45c1 /gcc/tree-vect-loop.cc | |
| parent | 3e8ee03edd018eed43444755f601cdb9d5931654 (diff) | |
| download | gcc-3a3fbec0a4d3f36de58df9ef0b3992a3ffb359c2.zip gcc-3a3fbec0a4d3f36de58df9ef0b3992a3ffb359c2.tar.gz gcc-3a3fbec0a4d3f36de58df9ef0b3992a3ffb359c2.tar.bz2 | |
LoongArch: Fixed an issue with the implementation of the template atomic_compare_and_swapsi.
If the hardware does not support LAMCAS, atomic_compare_and_swapsi needs to be
implemented through "ll.w+sc.w". In the implementation of the instruction sequence,
it is necessary to determine whether the two registers are equal.
Since LoongArch's comparison instructions do not distinguish between 32-bit
and 64-bit, the two operand registers that need to be compared are symbolically
extended, and one of the operand registers is obtained from memory through the
"ll.w" instruction, which can ensure that the symbolic expansion is carried out.
However, the value of the other operand register is not guaranteed to be the
value of the sign extension.
gcc/ChangeLog:
* config/loongarch/sync.md (atomic_cas_value_strong<mode>):
In loongarch64, a sign extension operation is added when
operands[2] is a register operand and the mode is SImode.
gcc/testsuite/ChangeLog:
* g++.target/loongarch/atomic-cas-int.C: New test.
Diffstat (limited to 'gcc/tree-vect-loop.cc')
0 files changed, 0 insertions, 0 deletions