RISC-V: Add testcases for scalar unsigned SAT_ADD form 2

After the middle-end support the form 2 of unsigned SAT_ADD and
the RISC-V backend implement the scalar .SAT_ADD, add more test
case to cover the form 2 of unsigned .SAT_ADD.

Form 2:

  #define SAT_ADD_U_2(T) \
  T sat_add_u_2_##T(T x, T y) \
  { \
    T ret; \
    T overflow = __builtin_add_overflow (x, y, &ret); \
    return (T)(-overflow) | ret; \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add test macro for form 2.
	* gcc.target/riscv/sat_u_add-10.c: New test.
	* gcc.target/riscv/sat_u_add-11.c: New test.
	* gcc.target/riscv/sat_u_add-12.c: New test.
	* gcc.target/riscv/sat_u_add-9.c: New test.
	* gcc.target/riscv/sat_u_add-run-10.c: New test.
	* gcc.target/riscv/sat_u_add-run-11.c: New test.
	* gcc.target/riscv/sat_u_add-run-12.c: New test.
	* gcc.target/riscv/sat_u_add-run-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions