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| author | Shaokun Zhang <zhangshaokun@hisilicon.com> | 2019-09-25 12:38:59 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2019-09-25 12:38:59 +0000 |
| commit | 761e6bb9f7d2bd782d93e46baebade2eb1f7d16e (patch) | |
| tree | c67de1fcd27ea5440bdfa1a5cdb272eacf721980 /gcc/tree-vect-loop.c | |
| parent | 21f7f9980c078080189ca78e4da56f0c26736946 (diff) | |
| download | gcc-761e6bb9f7d2bd782d93e46baebade2eb1f7d16e.zip gcc-761e6bb9f7d2bd782d93e46baebade2eb1f7d16e.tar.gz gcc-761e6bb9f7d2bd782d93e46baebade2eb1f7d16e.tar.bz2 | |
[AARCH64] Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC
The DCache clean & ICache invalidation requirements for instructions
to be data coherence are discoverable through new fields in CTR_EL0.
Let's support the two bits if they are enabled, the CPU core will
not execute the unnecessary DCache clean or Icache Invalidation
instructions.
2019-09-25 Shaokun Zhang <zhangshaokun@hisilicon.com>
* config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Add support for
CTR_EL0.IDC and CTR_EL0.DIC.
From-SVN: r276122
Diffstat (limited to 'gcc/tree-vect-loop.c')
0 files changed, 0 insertions, 0 deletions