aarch64: Avoid allocating FPRs to address registers [PR113623]

For something like:

void
foo (void)
{
  int *ptr;
  asm volatile ("%0" : "=w" (ptr));
  asm volatile ("%0" :: "m" (*ptr));
}

early-ra would allocate ptr to an FPR for the first asm, thus
leaving an FPR address in the second asm.  The address was then
reloaded by LRA to make it valid.

But early-ra shouldn't be allocating at all in that kind of
situation.  Doing so caused the ICE in the PR (with LDP fusion).

Fixed by making sure that we record address references as
GPR references.

gcc/
	PR target/113623
	* config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
	Mark all registers that occur in addresses as needing a GPR.

gcc/testsuite/
	PR target/113623
	* gcc.c-torture/compile/pr113623.c: New test.

0 files changed, 0 insertions, 0 deletions