RISC-V: Optimize local AVL propagation

I recently noticed that current VSETVL pass has a unnecessary restriction on local
AVL propgation.

Consider this following case:

+                      insn 1: vsetvli a5,a3,e8,mf4,ta,mu
+                      insn 2: vsetvli zero,a5,e32,m1,ta,ma
+                      ...
+                      vle32.v v1,0(a1)
+                      vsetvli a2,zero,e32,m1,ta,ma
+                      vadd.vv v1,v1,v1
+                      vsetvli zero,a5,e32,m1,ta,ma
+                      vse32.v v1,0(a0)
+                      ...
+                      insn 3: sub     a3,a3,a5
+                      ...

We failed to elide insn 2 (vsetvl insn) since insn 3 is modifying "a3" AVL.
Actually, we don't really care about insn 3 since we should only check and make sure
there is no insn between insn 1 and insn 2 that modifies "a3" AVL. Then, we can propgate
AVL "a3" from insn 1 to insn 2. Finally, insn 2 is eliminated.

After this patch:

+                      insn 1: vsetvli a5,a3,e8,mf4,ta,ma
+                      ...
+                      vle32.v v1,0(a1)
+                      vsetvli a2,zero,e32,m1,ta,ma
+                      vadd.vv v1,v1,v1
+                      vsetvli zero,a5,e32,m1,ta,ma
+                      vse32.v v1,0(a0)
+                      ...
+                      insn 3: sub     a3,a3,a5
+                      ...

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc
	(vector_insn_info::parse_insn): Add early break.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/vsetvl/avl_prop-1.c: New test.

0 files changed, 0 insertions, 0 deletions