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| author | Pan Li <pan2.li@intel.com> | 2023-10-23 15:45:12 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-10-23 16:00:32 +0800 |
| commit | 996785db50a4e2df0b0e892cfe39dcf4130fb87d (patch) | |
| tree | 07ae35617c709c8dce2c7ad19c164c2efae04c7d /gcc/tree-vect-loop-manip.cc | |
| parent | e1b1cba141aa1c7dadd0d4ac5ff93e3015fdffc0 (diff) | |
| download | gcc-996785db50a4e2df0b0e892cfe39dcf4130fb87d.zip gcc-996785db50a4e2df0b0e892cfe39dcf4130fb87d.tar.gz gcc-996785db50a4e2df0b0e892cfe39dcf4130fb87d.tar.bz2 | |
RISC-V: Bugfix for merging undef tmp register for trunc
For trunc function autovec, there will be one step like below take MU
for the merge operand.
rtx tmp = gen_reg_rtx (vec_int_mode);
emit_vec_cvt_x_f_rtz (tmp, op_1, mask, vec_fp_mode);
The MU will leave the tmp (aka dest register) register unmasked elements
unchanged and it is undefined here. This patch would like to adjust the
MU to MA.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_vec_cvt_x_f_rtz): Add insn type
arg.
(expand_vec_trunc): Take MA instead of MU for cvt_x_f_rtz.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc/tree-vect-loop-manip.cc')
0 files changed, 0 insertions, 0 deletions