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| author | Alex Coplan <alex.coplan@arm.com> | 2023-10-11 15:57:32 +0000 |
|---|---|---|
| committer | Alex Coplan <alex.coplan@arm.com> | 2023-10-19 11:12:23 +0100 |
| commit | 61ea0a89c6face2ce5651e4819adea5d9b613f3d (patch) | |
| tree | cf1c1a0d6f225e612128f4a9563226358298e77d /gcc/tree-vect-loop-manip.cc | |
| parent | cf776eebe86b8b75697de55a6a8ade72ce9f66c5 (diff) | |
| download | gcc-61ea0a89c6face2ce5651e4819adea5d9b613f3d.zip gcc-61ea0a89c6face2ce5651e4819adea5d9b613f3d.tar.gz gcc-61ea0a89c6face2ce5651e4819adea5d9b613f3d.tar.bz2 | |
aarch64, testsuite: Fix up pr71727.c
The test is trying to check that we don't use q-register stores with
-mstrict-align, so actually check specifically for that.
This is a prerequisite to avoid regressing:
scan-assembler-not "add\tx0, x0, :"
with the upcoming ldp fusion pass, as we change where the ldps are
formed such that a register is used rather than a symbolic (lo_sum)
address for the first load.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/pr71727.c: Adjust scan-assembler-not to
make sure we don't have q-register stores with -mstrict-align.
Diffstat (limited to 'gcc/tree-vect-loop-manip.cc')
0 files changed, 0 insertions, 0 deletions