[aarch64]: redefine aes patterns

This first patch removes aarch64 usage of the aese/aesmc and aesd/aesimc
fusions (i.e. aes fusion) implemented in the scheduler due to unpredictable
behaviour observed in cases such as:
- when register allocation goes bad (e.g. extra movs)
- aes operations with xor and zeroed keys among interleaved operations

A more stable version should be provided by instead doing the aes fusion
during the combine pass. Since the aese and aesd patterns have been
rewritten as encapsulating a xor operation, the existing combine fusion
patterns have also been updated. The purpose is to simplify the need of
having additional combine patterns for cases like the ones below:

For AESE (though it also applies to AESD as both have a xor operation):

    data = data ^ key;
    data = vaeseq_u8(data, zero);
    ---
    eor         v1.16b, v0.16b, v1.16b
    aese        v1.16b, v2.16b

Should mean and generate the same as:

    data = vaeseq_u8(data, key);
    ---
    aese        v1.16b, v0.16b

2019-07-09  Sylvia Taylor  <sylvia.taylor@arm.com>

	* config/aarch64/aarch64-simd.md
	(aarch64_crypto_aes<aes_op>v16qi): Redefine pattern with xor.
	(aarch64_crypto_aes<aesmc_op>v16qi): Remove attribute enabled.
	(*aarch64_crypto_aes<aes_op>v16qi_xor_combine): Remove both.
	(*aarch64_crypto_aese_fused,
	*aarch64_crypto_aesd_fused): Update to new definition.
	* config/aarch64/aarch64.c
	(aarch_macro_fusion_pair_p): Remove aese/aesmc fusion check.

	* gcc.target/aarch64/crypto-fuse-1.c: Remove.
	* gcc.target/aarch64/crypto-fuse-2.c: Remove.
	* gcc.target/aarch64/aes-fuse-1.c: New testcase.
	* gcc.target/aarch64/aes-fuse-2.c: New testcase.

From-SVN: r273304

0 files changed, 0 insertions, 0 deletions