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| author | Jim Wilson <jimw@sifive.com> | 2021-08-23 15:50:22 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2021-10-25 17:06:13 +0800 |
| commit | 283b1707f2373794c9ff724f01429586359f0b71 (patch) | |
| tree | ac1d6759d88f09336dc5873f7ae1429c56fc9fcb /gcc/tree-vect-data-refs.c | |
| parent | 149e217033f01410a9783c5cb2d020cf8334ae4c (diff) | |
| download | gcc-283b1707f2373794c9ff724f01429586359f0b71.zip gcc-283b1707f2373794c9ff724f01429586359f0b71.tar.gz gcc-283b1707f2373794c9ff724f01429586359f0b71.tar.bz2 | |
RISC-V: Implement instruction patterns for ZBA extension.
2021-10-25 Jim Wilson <jimw@sifive.com>
Kito Cheng <kito.cheng@sifive.com>
Jia-Wei Chen <jiawei@iscas.ac.cn>
gcc/ChangeLog:
* config/riscv/bitmanip.md (*zero_extendsidi2_bitmanip): New.
(*shNadd): Ditto.
(*shNadduw): Ditto.
(*add.uw): Ditto.
(*slliuw): Ditto.
(riscv_rtx_costs): Ditto.
* config/riscv/riscv.md: Include bitmanip.md
(type): Add bitmanip bype.
(zero_extendsidi2): Change to define_expand pattern.
(*zero_extendsidi2_internal): New.
(zero_extendsidi2_shifted): Disable for ZBA.
2021-10-25 Kito Cheng <kito.cheng@sifive.com>
Jia-Wei Chen <jiawei@iscas.ac.cn>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zba-adduw.c: New.
* gcc.target/riscv/zba-shNadd-01.c: Ditto.
* gcc.target/riscv/zba-shNadd-02.c: Ditto.
* gcc.target/riscv/zba-shNadd-03.c: Ditto.
* gcc.target/riscv/zba-slliuw.c: Ditto.
* gcc.target/riscv/zba-zextw.c: Ditto.
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Co-authored-by: Jia-Wei Chen <jiawei@iscas.ac.cn>
Diffstat (limited to 'gcc/tree-vect-data-refs.c')
0 files changed, 0 insertions, 0 deletions