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| author | Haochen Jiang <haochen.jiang@intel.com> | 2023-03-10 10:38:50 +0800 |
|---|---|---|
| committer | Haochen Jiang <haochen.jiang@intel.com> | 2023-04-20 09:32:55 +0800 |
| commit | 4246611d1915f1664c01f286dbeb946dd06e2a4d (patch) | |
| tree | c6f39ca67f78eeac462324656fec52f47e09511a /gcc/tree-stdarg.cc | |
| parent | e8571019066d9820c5cd4b3019b816203d438e83 (diff) | |
| download | gcc-4246611d1915f1664c01f286dbeb946dd06e2a4d.zip gcc-4246611d1915f1664c01f286dbeb946dd06e2a4d.tar.gz gcc-4246611d1915f1664c01f286dbeb946dd06e2a4d.tar.bz2 | |
i386: Add PCLMUL dependency for VPCLMULQDQ
Currently in GCC, the 128 bit intrin for instruction vpclmulqdq is
under PCLMUL ISA. Because there is no dependency between ISA set PCLMUL
and VPCLMULQDQ, The 128 bit intrin is not available when we just use
compiler flag -mvpclmulqdq. But it should according to Intel SDM.
Since VPCLMULQDQ is a VEX/EVEX promotion for PCLMUL, it is natural to
add dependency between them.
Also, with -mvpclmulqdq, we can use ymm under VEX encoding, so
VPCLMULQDQ should imply AVX.
gcc/ChangeLog:
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA_VPCLMULQDQ_SET):
Add OPTION_MASK_ISA_PCLMUL_SET and OPTION_MASK_ISA_AVX_SET.
(OPTION_MASK_ISA_AVX_UNSET):
Add OPTION_MASK_ISA_VPCLMULQDQ_UNSET.
(OPTION_MASK_ISA_PCLMUL_UNSET): Ditto.
* config/i386/i386.md (vpclmulqdqvl): New.
* config/i386/sse.md (pclmulqdq): Add evex encoding.
* config/i386/vpclmulqdqintrin.h: Remove redudant avx target
push.
gcc/testsuite/ChangeLog:
* gcc.target/i386/vpclmulqdq.c: Add compile test for xmm.
Diffstat (limited to 'gcc/tree-stdarg.cc')
0 files changed, 0 insertions, 0 deletions