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| author | Uros Bizjak <uros@gcc.gnu.org> | 2012-05-09 20:06:47 +0200 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2012-05-09 20:06:47 +0200 |
| commit | 20f9034bc38de755016d3858e23ee438abcfc80b (patch) | |
| tree | 2fad70c416fc89d99cae46f4c14179415943c6c4 /gcc/tree-stdarg.c | |
| parent | eac188c5bcb1ed4f3fd61de2de2590dece32be2b (diff) | |
| download | gcc-20f9034bc38de755016d3858e23ee438abcfc80b.zip gcc-20f9034bc38de755016d3858e23ee438abcfc80b.tar.gz gcc-20f9034bc38de755016d3858e23ee438abcfc80b.tar.bz2 | |
re PR target/44141 (Redundant loads and stores generated for AMD bdver1 target)
PR target/44141
* config/i386/i386.c (ix86_expand_vector_move_misalign): Do not handle
128 bit vectors specially for TARGET_AVX. Emit sse2_movupd and
sse_movupd RTXes for TARGET_AVX, TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
or when optimizing for size.
* config/i386/sse.md (*mov<mode>_internal): Remove
TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL handling from asm output code.
Calculate "mode" attribute according to optimize_function_for_size_p
and TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL flag.
(*<sse>_movu<ssemodesuffix><avxsizesuffix>): Choose asm template
depending on the mode of the instruction. Calculate "mode" attribute
according to optimize_function_for_size_p, TARGET_SSE_TYPELESS_STORES
and TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL flags.
(*<sse2>_movdqu<avxsizesuffix>): Ditto.
From-SVN: r187347
Diffstat (limited to 'gcc/tree-stdarg.c')
0 files changed, 0 insertions, 0 deletions