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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:02:54 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:02:54 -0700 |
| commit | dfa61b9ed06d71901c4c430caa89820972ad68fe (patch) | |
| tree | b6d4e739c2425a70e5b2bb5093622885b42b5af3 /gcc/tree-ssa.c | |
| parent | 2e97dfdd542fba50566fd5d3dc87207d968d87d2 (diff) | |
| download | gcc-dfa61b9ed06d71901c4c430caa89820972ad68fe.zip gcc-dfa61b9ed06d71901c4c430caa89820972ad68fe.tar.gz gcc-dfa61b9ed06d71901c4c430caa89820972ad68fe.tar.bz2 | |
i386: Allow MMX register modes in SSE registers
In 64-bit mode, SSE2 can be used to emulate MMX instructions without
3DNOW. We can use SSE2 to support MMX register modes.
PR target/89021
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE.
* config/i386/i386.c (ix86_set_reg_reg_cost): Add support for
TARGET_MMX_WITH_SSE with VALID_MMX_REG_MODE.
(ix86_vector_mode_supported_p): Likewise.
* config/i386/i386.h (TARGET_MMX_WITH_SSE): New.
From-SVN: r271213
Diffstat (limited to 'gcc/tree-ssa.c')
0 files changed, 0 insertions, 0 deletions