diff options
| author | Jakub Jelinek <jakub@redhat.com> | 2018-05-02 23:56:17 +0200 |
|---|---|---|
| committer | Jakub Jelinek <jakub@gcc.gnu.org> | 2018-05-02 23:56:17 +0200 |
| commit | 31aa23df38a66c429d08c06a0005eccecc9234dc (patch) | |
| tree | da4886e607b08410f158790f4f8e9ced6de28a7a /gcc/tree-ssa-threadupdate.c | |
| parent | 019808c95c540a830a64c132257bde018abf6a1e (diff) | |
| download | gcc-31aa23df38a66c429d08c06a0005eccecc9234dc.zip gcc-31aa23df38a66c429d08c06a0005eccecc9234dc.tar.gz gcc-31aa23df38a66c429d08c06a0005eccecc9234dc.tar.bz2 | |
re PR target/85582 (wrong code at -O1 and above on x86_64-linux-gnu in 32-bit mode)
PR target/85582
* config/i386/i386.md (*ashl<dwi>3_doubleword_mask,
*ashl<dwi>3_doubleword_mask_1, *<shift_insn><dwi>3_doubleword_mask,
*<shift_insn><dwi>3_doubleword_mask_1): In condition require that
the highest significant bit of the shift count mask is clear. In
check whether and[sq]i3 is needed verify that all significant bits
of the shift count other than the highest are set.
* gcc.c-torture/execute/pr85582-3.c: New test.
From-SVN: r259862
Diffstat (limited to 'gcc/tree-ssa-threadupdate.c')
0 files changed, 0 insertions, 0 deletions