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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2017-01-04 04:32:48 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2017-01-04 04:32:48 +0000 |
| commit | 60fb638f9c08e2cf73605fc5a60531215098a82d (patch) | |
| tree | b58e5f12cc14d7b64cda24d04cebfcef8d6d4907 /gcc/tree-ssa-threadupdate.c | |
| parent | c671a0d674de28574cad46b83ea7e141b7297cbd (diff) | |
| download | gcc-60fb638f9c08e2cf73605fc5a60531215098a82d.zip gcc-60fb638f9c08e2cf73605fc5a60531215098a82d.tar.gz gcc-60fb638f9c08e2cf73605fc5a60531215098a82d.tar.bz2 | |
re PR target/78900 (ICE in gcc.target/powerpc/signbit-3.c)
[gcc]
2016-12-30 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/78900
* config/rs6000/rs6000.c (rs6000_split_signbit): Change some
assertions. Add support for doing the signbit if the IEEE 128-bit
floating point value is in a GPR.
* config/rs6000/rs6000.md (Fsignbit): Delete.
(signbit<mode>2_dm): Delete using <Fsignbit> and just use "wa".
Update the length attribute if the value is in a GPR.
(signbit<mode>2_dm_<su>ext): Add combiner pattern to eliminate
the sign or zero extension instruction, since the value is always
0/1.
(signbit<mode>2_dm2): Delete using <Fsignbit>.
2017-01-03 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/78953
* config/rs6000/vsx.md (vsx_extract_<mode>_store_p9): If we are
extracting SImode to a GPR register so that we can generate a
store, limit the vector to be in a traditional Altivec register
for the vextuwrx instruction.
[gcc/testsuite]
2017-01-03 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/78953
* gcc.target/powerpc/pr78953.c: New test.
From-SVN: r244044
Diffstat (limited to 'gcc/tree-ssa-threadupdate.c')
0 files changed, 0 insertions, 0 deletions