diff options
| author | liuhongt <hongtao.liu@intel.com> | 2021-09-10 10:15:58 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2021-09-28 11:00:29 +0800 |
| commit | 9cfb95f9b92326e86e99b50350ebf04fa9cd2477 (patch) | |
| tree | fabd1771c0d17d5f629c29d5d9a941a98979fa45 /gcc/tree-ssa-threadupdate.c | |
| parent | 3540429be7ad1085af83600483908b621078fb6f (diff) | |
| download | gcc-9cfb95f9b92326e86e99b50350ebf04fa9cd2477.zip gcc-9cfb95f9b92326e86e99b50350ebf04fa9cd2477.tar.gz gcc-9cfb95f9b92326e86e99b50350ebf04fa9cd2477.tar.bz2 | |
Relax condition of (vec_concat:M(vec_select op0 idx0)(vec_select op0 idx1)) to allow different modes between op0 and M, but have same inner mode.
This will enable optimization for below pattern.
(set (reg:V2DF 87 [ xx ])
(vec_concat:V2DF (vec_select:DF (reg:V4DF 92)
(parallel [
(const_int 2 [0x2])
]))
(vec_select:DF (reg:V4DF 92)
(parallel [
(const_int 3 [0x3])
]))))
gcc/ChangeLog:
* simplify-rtx.c
(simplify_context::simplify_binary_operation_1): Relax
condition of simplifying (vec_concat:M (vec_select op0
index0)(vec_select op1 index1)) to allow different modes
between op0 and M, but have same inner mode.
gcc/testsuite/ChangeLog:
* gcc.target/i386/vect-rebuild.c: Adjust testcases.
* gcc.target/i386/avx512f-vect-rebuild.c: New test.
Diffstat (limited to 'gcc/tree-ssa-threadupdate.c')
0 files changed, 0 insertions, 0 deletions