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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2013-11-22 17:24:32 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2013-11-22 17:24:32 +0000 |
| commit | 7d20ca6146e4ee527f9c48fb96d0ca83d3fb68c3 (patch) | |
| tree | 1c7c37213eaf3dc6a8afb834c94eda9a56ec5174 /gcc/tree-ssa-threadedge.c | |
| parent | 237c8b9d2f2cc0858ed6950f366cdb6d39f5c900 (diff) | |
| download | gcc-7d20ca6146e4ee527f9c48fb96d0ca83d3fb68c3.zip gcc-7d20ca6146e4ee527f9c48fb96d0ca83d3fb68c3.tar.gz gcc-7d20ca6146e4ee527f9c48fb96d0ca83d3fb68c3.tar.bz2 | |
re PR target/59054 (Powerpc -O0 -mcpu=power7 generates sub-optimal code to load 0)
2013-11-22 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/59054
* gcc.target/powerpc/direct-move.h (VSX_REG_ATTR): Allow test to
specify an appropriate register class for VSX operations.
(load_vsx): Use it.
(load_gpr_to_vsx): Likewise.
(load_vsx_to_gpr): Likewise.
* gcc.target/powerpc/direct-move-vint1.c: Use an appropriate
register class for VSX registers that the type can handle. Remove
checks for explicit number of instructions generated, just check
if the instruction is generated.
* gcc.target/powerpc/direct-move-vint2.c: Likewise.
* gcc.target/powerpc/direct-move-float1.c: Likewise.
* gcc.target/powerpc/direct-move-float2.c: Likewise.
* gcc.target/powerpc/direct-move-double1.c: Likewise.
* gcc.target/powerpc/direct-move-double2.c: Likewise.
* gcc.target/powerpc/direct-move-long1.c: Likewise.
* gcc.target/powerpc/direct-move-long2.c: Likewise.
* gcc.target/powerpc/pr59054.c: Remove duplicate code.
* gcc.target/powerpc/bool3-av.c: Limit to 64-bit mode for now.
* gcc.target/powerpc/bool3-p7.c: Likewise.
* gcc.target/powerpc/bool3-p8.c: Likewise.
* gcc.target/powerpc/p8vector-ldst.c: Just check that the
appropriate instructions are generated, don't check the count.
From-SVN: r205278
Diffstat (limited to 'gcc/tree-ssa-threadedge.c')
0 files changed, 0 insertions, 0 deletions