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| author | Thomas Preud'homme <thomas.preudhomme@arm.com> | 2016-10-27 10:19:13 +0000 |
|---|---|---|
| committer | Thomas Preud'homme <thopre01@gcc.gnu.org> | 2016-10-27 10:19:13 +0000 |
| commit | 33cab74617734fdda5b39bd645d13361cd92af23 (patch) | |
| tree | 3908dbafeb8193cf3995942698b7b0604f5cb7a7 /gcc/tree-ssa-threadedge.c | |
| parent | b5300487f1c9c92f1f5bbe1063a0240154815f47 (diff) | |
| download | gcc-33cab74617734fdda5b39bd645d13361cd92af23.zip gcc-33cab74617734fdda5b39bd645d13361cd92af23.tar.gz gcc-33cab74617734fdda5b39bd645d13361cd92af23.tar.bz2 | |
Adapt other atomic operations to ARMv8-M Baseline
2016-10-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm.c (arm_split_atomic_op): Add function comment. Add
logic to to decide whether to copy over old value to register for new
value.
* config/arm/sync.md: Add comments explaning why mode and code
attribute are not defined in iterators.md
(thumb1_atomic_op_str): New code attribute.
(thumb1_atomic_newop_str): Likewise.
(thumb1_atomic_fetch_op_str): Likewise.
(thumb1_atomic_fetch_newop_str): Likewise.
(thumb1_atomic_fetch_oldop_str): Likewise.
(atomic_exchange<mode>): Add new ARMv8-M Baseline only alternatives to
mirror the more restrictive constraints of the Thumb-1 insns after
split compared to Thumb-2 counterpart insns.
(atomic_<sync_optab><mode>): Likewise. Add comment to keep constraints
in sync with non atomic version.
(atomic_nand<mode>): Likewise.
(atomic_fetch_<sync_optab><mode>): Likewise.
(atomic_fetch_nand<mode>): Likewise.
(atomic_<sync_optab>_fetch<mode>): Likewise.
(atomic_nand_fetch<mode>): Likewise.
* config/arm/thumb1.md (thumb1_addsi3): Add comment to keep contraint
in sync with atomic version.
(thumb1_subsi3_insn): Likewise.
(thumb1_andsi3_insn): Likewise.
(thumb1_iorsi3_insn): Likewise.
(thumb1_xorsi3_insn): Likewise.
From-SVN: r241614
Diffstat (limited to 'gcc/tree-ssa-threadedge.c')
0 files changed, 0 insertions, 0 deletions