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| author | Richard Earnshaw <rearnsha@arm.com> | 2013-09-10 16:46:55 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2013-09-10 16:46:55 +0000 |
| commit | d742ff4ba1609fe71d0a9396483b95d375e4599a (patch) | |
| tree | 0de0c179386f1b6a4d999a5b2ffd8cee0ff882fd /gcc/tree-ssa-threadedge.c | |
| parent | 1329f0c4e27f29cef728a9ab0329e1dd287a7812 (diff) | |
| download | gcc-d742ff4ba1609fe71d0a9396483b95d375e4599a.zip gcc-d742ff4ba1609fe71d0a9396483b95d375e4599a.tar.gz gcc-d742ff4ba1609fe71d0a9396483b95d375e4599a.tar.bz2 | |
re PR target/58361 (Wrong floating point code generated for ARM target)
PR target/58361
* arm/vfp.md (combine_vcvt_f32_<FCVTI32typename>): Fix pattern to
support conditional execution.
(combine_vcvt_f64_<FCVTI32typename>): Likewise.
From-SVN: r202475
Diffstat (limited to 'gcc/tree-ssa-threadedge.c')
0 files changed, 0 insertions, 0 deletions