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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2013-09-05 15:53:37 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2013-09-05 15:53:37 +0000 |
| commit | fe6f68e2bb8ba87612605cc0f6b55b188f002491 (patch) | |
| tree | 8c8a2e49078948520f48b3ae7e0e4b606af7eb54 /gcc/tree-ssa-threadedge.c | |
| parent | 6e4150e1d402f8d1c8f23dfbdb5157978133c42f (diff) | |
| download | gcc-fe6f68e2bb8ba87612605cc0f6b55b188f002491.zip gcc-fe6f68e2bb8ba87612605cc0f6b55b188f002491.tar.gz gcc-fe6f68e2bb8ba87612605cc0f6b55b188f002491.tar.bz2 | |
[AArch64] Fix categorisation of the frecp* insns.
gcc/
* config/aarch64/aarch64.md
(type): Remove frecpe, frecps, frecpx.
(aarch64_frecp<FRECP:frecp_suffix><mode>): Move to aarch64-simd.md,
fix to be a TARGET_SIMD instruction.
(aarch64_frecps): Remove.
* config/aarch64/aarch64-simd.md
(aarch64_frecp<FRECP:frecp_suffix><mode>): New, moved from aarch64.md
(aarch64_frecps<mode>): Handle all float/vector of float modes.
From-SVN: r202292
Diffstat (limited to 'gcc/tree-ssa-threadedge.c')
0 files changed, 0 insertions, 0 deletions