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| author | Andrew Burgess <andrew.burgess@embecosm.com> | 2019-10-16 22:01:25 +0100 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2019-10-16 14:01:25 -0700 |
| commit | 3599dfbaa22b95ecabd3da9ba68ad4bb4f1124a4 (patch) | |
| tree | 42d8c7d19e6372a7740e691f200a2dc3d658af37 /gcc/tree-ssa-strlen.c | |
| parent | 2fcb55d11f4167b966151057c121d0a47914c5c8 (diff) | |
| download | gcc-3599dfbaa22b95ecabd3da9ba68ad4bb4f1124a4.zip gcc-3599dfbaa22b95ecabd3da9ba68ad4bb4f1124a4.tar.gz gcc-3599dfbaa22b95ecabd3da9ba68ad4bb4f1124a4.tar.bz2 | |
RISC-V: Include more registers in SIBCALL_REGS.
This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19.
This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS. It
also adds the missing riscv_regno_to_class change.
Tested with cross riscv32-elf and riscv64-linux toolchain build and check.
There were no regressions. I see about a 0.01% code size reduction for the
C and libstdc++ libraries.
gcc/
* config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
regs to SIBCALL_REGS.
* config/riscv/riscv.c (riscv_regno_to_class): Change argument
passing regs to SIBCALL_REGS.
Co-Authored-By: Jim Wilson <jimw@sifive.com>
From-SVN: r277082
Diffstat (limited to 'gcc/tree-ssa-strlen.c')
0 files changed, 0 insertions, 0 deletions