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| author | Richard Sandiford <richard.sandiford@arm.com> | 2021-11-04 08:28:44 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2021-11-04 08:28:44 +0000 |
| commit | 518f865f4babf3ab9160b37fa971e9078434f723 (patch) | |
| tree | 7b6dd77e9b45f71b5b73ae220577613ec7124b93 /gcc/tree-ssa-sccvn.c | |
| parent | 95318d469f4d293446b4fd38d527fd5d64ce0b70 (diff) | |
| download | gcc-518f865f4babf3ab9160b37fa971e9078434f723.zip gcc-518f865f4babf3ab9160b37fa971e9078434f723.tar.gz gcc-518f865f4babf3ab9160b37fa971e9078434f723.tar.bz2 | |
simplify-rtx: Fix vec_select index check
Vector lane indices follow memory (array) order, so lane 0 corresponds
to the high element rather than the low element on big-endian targets.
This was causing quite a few execution failures on aarch64_be,
such as gcc.c-torture/execute/pr47538.c.
gcc/
* simplify-rtx.c (simplify_context::simplify_gen_vec_select): Assert
that the operand has a vector mode. Use subreg_lowpart_offset
to test whether an index corresponds to the low part.
gcc/testsuite/
* gcc.dg/rtl/aarch64/big-endian-cse-1.c: New test.
Diffstat (limited to 'gcc/tree-ssa-sccvn.c')
0 files changed, 0 insertions, 0 deletions