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| author | Vineet Gupta <vgupta@synopsys.com> | 2019-01-23 11:04:19 +0000 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@gcc.gnu.org> | 2019-01-23 12:04:19 +0100 |
| commit | b3e5901b625df90e3618b2e5a06cccc36cd84b6a (patch) | |
| tree | 76b5ee0771dae452216e9af6b4a27080b182af63 /gcc/tree-ssa-reassoc.c | |
| parent | 3f5d2012fb0ba2306b8f0799b50ccee6dc3762fc (diff) | |
| download | gcc-b3e5901b625df90e3618b2e5a06cccc36cd84b6a.zip gcc-b3e5901b625df90e3618b2e5a06cccc36cd84b6a.tar.gz gcc-b3e5901b625df90e3618b2e5a06cccc36cd84b6a.tar.bz2 | |
[ARC] atomics: Add operand to DMB instruction
Atomics use DMB instruction to enforce ordering of loads/stores.
Currently gcc generates DMB w/o any arg which is a no-op. Fix that by
generating DMB 3 which enforces R+W ordering. It is stricter than what
acq/rel expect, but there's no other way.
gcc/
2019-xx-xx Vineet Gupta <vgupta@synopsys.com>
* config/arc/atomic.md: Add operand to DMB instruction
From-SVN: r268181
Diffstat (limited to 'gcc/tree-ssa-reassoc.c')
0 files changed, 0 insertions, 0 deletions