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| author | Tamar Christina <tamar.christina@arm.com> | 2022-08-12 12:28:41 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2022-08-12 12:28:41 +0100 |
| commit | f4ff20d464f90c85919ce2e7fa63e204dcda4e40 (patch) | |
| tree | 179246fd5aa1757653a451341bcea38cdf3d0198 /gcc/tree-ssa-phiopt.cc | |
| parent | 7e3b45befdbbf1a1f9ff728fa2bac31b4756907c (diff) | |
| download | gcc-f4ff20d464f90c85919ce2e7fa63e204dcda4e40.zip gcc-f4ff20d464f90c85919ce2e7fa63e204dcda4e40.tar.gz gcc-f4ff20d464f90c85919ce2e7fa63e204dcda4e40.tar.bz2 | |
sve: Fix fcmuo combine patterns [PR106524]
There's no encoding for fcmuo with zero. This restricts the combine patterns
from accepting zero registers.
gcc/ChangeLog:
PR target/106524
* config/aarch64/aarch64-sve.md (*fcmuo<mode>_nor_combine,
*fcmuo<mode>_bic_combine): Don't accept comparisons against zero.
gcc/testsuite/ChangeLog:
PR target/106524
* gcc.target/aarch64/sve/pr106524.c: New test.
Diffstat (limited to 'gcc/tree-ssa-phiopt.cc')
0 files changed, 0 insertions, 0 deletions