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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-09-24 11:17:01 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-09-25 14:11:39 +0800 |
| commit | 9d5f20fc4a6b3254d2d379309193da4be2747987 (patch) | |
| tree | 46bb095cf0b416eb7d1833cdaf1434b84e1e30ba /gcc/tree-ssa-phiopt.cc | |
| parent | a65b38e361320e0aa45adbc969c704385ab1f45b (diff) | |
| download | gcc-9d5f20fc4a6b3254d2d379309193da4be2747987.zip gcc-9d5f20fc4a6b3254d2d379309193da4be2747987.tar.gz gcc-9d5f20fc4a6b3254d2d379309193da4be2747987.tar.bz2 | |
RISC-V: Fix AVL/VL bug of VSETVL PASS[PR111548]
This patch fixes that AVL/VL reg incorrect fetch in VSETVL PASS.
C/C++ regression passed.
But gfortran didn't run yet. I am still finding a way to run it.
Will commit it when I pass the fortran regression.
PR target/111548
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (earliest_pred_can_be_fused_p): Bugfix
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr111548.c: New test.
Diffstat (limited to 'gcc/tree-ssa-phiopt.cc')
0 files changed, 0 insertions, 0 deletions