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author | Andrew Pinski <apinski@marvell.com> | 2023-04-28 05:22:34 +0000 |
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committer | Andrew Pinski <apinski@marvell.com> | 2023-05-02 14:10:19 -0700 |
commit | 7cc33d12dca84befde69259a17fab8224e2e4025 (patch) | |
tree | c220f6e80cc25d3c66e6891f38516a57b680c7cc /gcc/tree-ssa-phiopt.cc | |
parent | f9861511a1fa0f9e386f3f7bcee84b6e3ca3c579 (diff) | |
download | gcc-7cc33d12dca84befde69259a17fab8224e2e4025.zip gcc-7cc33d12dca84befde69259a17fab8224e2e4025.tar.gz gcc-7cc33d12dca84befde69259a17fab8224e2e4025.tar.bz2 |
target: [PR109657] (a ? -1 : 0) | b could be optimized better for aarch64
There is no canonical form for this case defined. So the aarch64 backend needs
a pattern to match both of these forms.
The forms are:
(set (reg/i:SI 0 x0)
(if_then_else:SI (eq (reg:CC 66 cc)
(const_int 0 [0]))
(reg:SI 97)
(const_int -1 [0xffffffffffffffff])))
and
(set (reg/i:SI 0 x0)
(ior:SI (neg:SI (ne:SI (reg:CC 66 cc)
(const_int 0 [0])))
(reg:SI 102)))
Currently the aarch64 backend matches the first form so this
patch adds a insn_and_split to match the second form and
convert it to the first form.
OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions
PR target/109657
gcc/ChangeLog:
* config/aarch64/aarch64.md (*cmov<mode>_insn_m1): New
insn_and_split pattern.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/csinv-2.c: New test.
Diffstat (limited to 'gcc/tree-ssa-phiopt.cc')
0 files changed, 0 insertions, 0 deletions