diff options
author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-04-23 19:17:52 +0800 |
---|---|---|
committer | Kito Cheng <kito.cheng@sifive.com> | 2023-04-24 14:18:17 +0800 |
commit | 4eae76d10433b12bdb6944c2b3be818ccc3b5986 (patch) | |
tree | cd3d6c93f2361d0216dff5431cc15ff6fa6f2f53 /gcc/tree-ssa-phiopt.cc | |
parent | 8311c26757657fe8ffa28ca1539d02d141bb8292 (diff) | |
download | gcc-4eae76d10433b12bdb6944c2b3be818ccc3b5986.zip gcc-4eae76d10433b12bdb6944c2b3be818ccc3b5986.tar.gz gcc-4eae76d10433b12bdb6944c2b3be818ccc3b5986.tar.bz2 |
RISC-V: Optimize fault only first load
V2 patch for: https://patchwork.sourceware.org/project/gcc/patch/20230330012804.110539-1-juzhe.zhong@rivai.ai/
which has been reviewed.
This patch address Jeff's comment, refine ChangeLog to give more
clear information.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: New unspec to refine fault first load pattern.
* config/riscv/vector.md: Refine fault first load pattern to erase avl from instructions
with the fault first load property.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/ffload-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/ffload-2.c: New test.
* gcc.target/riscv/rvv/vsetvl/ffload-3.c: New test.
* gcc.target/riscv/rvv/vsetvl/ffload-5.c: New test.
* gcc.target/riscv/rvv/vsetvl/ffload-6.c: New test.
* gcc.target/riscv/rvv/vsetvl/ffload-7.c: New test.
Diffstat (limited to 'gcc/tree-ssa-phiopt.cc')
0 files changed, 0 insertions, 0 deletions