RISC-V: Enable SLP un-order reduction

This patch is to enable SLP un-order reduction autao-vectorization

Consider this following case:

int __attribute__((noipa))
add_loop (int *x, int n, int res)
{
  for (int i = 0; i < n; ++i)
    {
      res += x[i * 2];
      res += x[i * 2 + 1];
    }
  return res;
}

--param riscv-autovec-preference=scalable -fopt-info-vec-missed:
<source>:4:21: missed: couldn't vectorize loop
<source>:4:21: missed: unsupported SLP instances

After this patch:

add_loop:
	ble	a1,zero,.L5
	csrr	a6,vlenb
	srli	a4,a6,2
	slli	a1,a1,1
	neg	a7,a4
	vsetvli	t1,zero,e32,m1,ta,ma
	vmv.v.i	v2,0
	vslide1up.vx	v1,v2,a2   -----------> generated by VEC_SHL_INSERT
.L4:
	mv	a3,a1
	mv	a5,a1
	bleu	a1,a4,.L3
	mv	a5,a4
.L3:
	vsetvli	zero,a5,e32,m1,tu,ma
	add	a1,a1,a7
	vle32.v	v2,0(a0)
	add	a0,a0,a6
	vadd.vv	v1,v1,v2
	bgtu	a3,a4,.L4
	vsetivli	zero,1,e32,m1,ta,ma
	vmv.v.i	v2,0
	vsetvli	t1,zero,e32,m1,ta,ma
	vredsum.vs	v1,v1,v2
	vmv.x.s	a0,v1
	ret
.L5:
	mv	a0,a2
	ret

gcc/ChangeLog:

	* config/riscv/autovec.md (vec_shl_insert_<mode>): New patterns.
	* config/riscv/riscv-v.cc (shuffle_compress_patterns): Fix bugs.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/reduc/reduc-5.c: New test.
	* gcc.target/riscv/rvv/autovec/reduc/reduc-6.c: New test.
	* gcc.target/riscv/rvv/autovec/reduc/reduc-7.c: New test.
	* gcc.target/riscv/rvv/autovec/reduc/reduc-8.c: New test.
	* gcc.target/riscv/rvv/autovec/reduc/reduc-9.c: New test.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c: New test.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c: New test.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c: New test.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c: New test.
	* gcc.target/riscv/rvv/autovec/reduc/reduc_run-9.c: New test.

0 files changed, 0 insertions, 0 deletions