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| author | Feng Wang <wangfeng@eswincomputing.com> | 2023-04-15 10:11:15 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-04-17 11:52:49 -0600 |
| commit | 0ccf520d349a82dafca0deb3d307a1080e8589a0 (patch) | |
| tree | e7c642ee9d3b35b20b7fdca84f319de0e1985ce0 /gcc/tree-ssa-phiopt.cc | |
| parent | f46ab321399f9b6b357a9f2bf399b708867cea54 (diff) | |
| download | gcc-0ccf520d349a82dafca0deb3d307a1080e8589a0.zip gcc-0ccf520d349a82dafca0deb3d307a1080e8589a0.tar.gz gcc-0ccf520d349a82dafca0deb3d307a1080e8589a0.tar.bz2 | |
RISC-V: Optimze the reverse conditions of rotate shift
gcc/ChangeLog:
* config/riscv/bitmanip.md (rotrsi3_sext): Support generating
roriw for constant counts.
* rtl.h (reverse_rotate_by_imm_p): Add function declartion
* simplify-rtx.cc (reverse_rotate_by_imm_p): New function.
(simplify_context::simplify_binary_operation_1): Use it.
* expmed.cc (expand_shift_1): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-rol-ror-04.c: New test.
* gcc.target/riscv/zbb-rol-ror-05.c: New test.
* gcc.target/riscv/zbb-rol-ror-06.c: New test.
* gcc.target/riscv/zbb-rol-ror-07.c: New test.
Diffstat (limited to 'gcc/tree-ssa-phiopt.cc')
0 files changed, 0 insertions, 0 deletions