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authorPatrick O'Neill <patrick@rivosinc.com>2023-04-07 10:44:09 -0700
committerPatrick O'Neill <patrick@rivosinc.com>2023-05-02 13:08:04 -0700
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RISC-V: Weaken mem_thread_fence
This change brings atomic fences in line with table A.6 of the ISA manual. Relax mem_thread_fence according to the memmodel given. 2023-04-27 Patrick O'Neill <patrick@rivosinc.com> gcc/ChangeLog: * config/riscv/sync.md (mem_thread_fence_1): Change fence depending on the given memory model. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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