RISC-V: Implement SAT_ADD for signed integer vector

This patch would like to implement the ssadd for vector integer.  Aka
form 1 of ssadd vector.

Form 1:
  #define DEF_VEC_SAT_S_ADD_FMT_1(T, UT, MIN, MAX)                     \
  void __attribute__((noinline))                                       \
  vec_sat_s_add_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        T sum = (UT)x + (UT)y;                                         \
        out[i] = (x ^ y) < 0                                           \
          ? sum                                                        \
          : (sum ^ x) >= 0                                             \
            ? sum                                                      \
            : x < 0 ? MIN : MAX;                                       \
      }                                                                \
  }

DEF_VEC_SAT_S_ADD_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX)

Before this patch:
vec_sat_s_add_int64_t_fmt_1:
  ...
  vsetvli  t1,zero,e64,m1,ta,mu
  vadd.vv  v3,v1,v2
  vxor.vv  v0,v1,v3
  vmslt.vi v0,v0,0
  vxor.vv  v2,v1,v2
  vmsge.vi v2,v2,0
  vmand.mm v0,v0,v2
  vsra.vx  v1,v1,t3
  vxor.vv  v3,v1,v4,v0.t
  ...

After this patch:
vec_sat_s_add_int64_t_fmt_1:
  ...
  vsetvli  a6,zero,e64,m1,ta,ma
  vsadd.vv v1,v1,v2
  ...

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/ChangeLog:

	* config/riscv/autovec.md (ssadd<mode>3): Add new pattern for
	signed integer vector SAT_ADD.
	* config/riscv/riscv-protos.h (expand_vec_ssadd): Add new func
	decl for vector ssadd expanding.
	* config/riscv/riscv-v.cc (expand_vec_ssadd): Add new func impl
	to expand vector ssadd pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: Add test
	data for vector ssadd.
	* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper
	macros.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-3.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-4.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions