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| author | Uros Bizjak <uros@gcc.gnu.org> | 2017-12-21 20:00:28 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2017-12-21 20:00:28 +0100 |
| commit | cb4b152d88b9c77f552345917601d401010dc4b3 (patch) | |
| tree | b50c571c96b42119ec68231cc9711e0a520dcfc9 /gcc/tree-ssa-phiopt.c | |
| parent | 056cf43428e87bff0703ab4a6ec3558a90328be4 (diff) | |
| download | gcc-cb4b152d88b9c77f552345917601d401010dc4b3.zip gcc-cb4b152d88b9c77f552345917601d401010dc4b3.tar.gz gcc-cb4b152d88b9c77f552345917601d401010dc4b3.tar.bz2 | |
re PR target/83467 (ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv)
PR target/83467
* config/i386/i386.md (*ashl<mode>3_mask): Add operand
constraints to operand 2.
(*ashl<mode>3_mask_1): Ditto.
(*<shift_insn><mode>3_mask): Ditto.
(*<shift_insn><mode>3_mask_1): Ditto.
(*<rotate_insn><mode>3_mask): Ditto.
(*<rotate_insn><mode>3_mask_1): Ditto.
testsuite/ChangeLog:
PR target/83467
* gcc.target/i386/pr83467-1.c: New test.
* gcc.target/i386/pr83467-2.c: Ditto.
From-SVN: r255949
Diffstat (limited to 'gcc/tree-ssa-phiopt.c')
0 files changed, 0 insertions, 0 deletions