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| author | Tejas Belagod <tejas.belagod@arm.com> | 2013-01-25 11:35:03 +0000 |
|---|---|---|
| committer | Tejas Belagod <belagod@gcc.gnu.org> | 2013-01-25 11:35:03 +0000 |
| commit | b7d7d917bd3ec775d21abfe4eab582de3cf461c7 (patch) | |
| tree | 46cc3c9053ddcc8bc08ce8e8b61958dc8bee498f /gcc/tree-ssa-phiopt.c | |
| parent | 556f9906c548af7332f7f274f9e05cacfaeb64a6 (diff) | |
| download | gcc-b7d7d917bd3ec775d21abfe4eab582de3cf461c7.zip gcc-b7d7d917bd3ec775d21abfe4eab582de3cf461c7.tar.gz gcc-b7d7d917bd3ec775d21abfe4eab582de3cf461c7.tar.bz2 | |
aarch64-simd-builtins.def: Separate sq<r>dmulh_lane entries into lane and laneq entries.
2013-01-25 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Separate sq<r>dmulh_lane
entries into lane and laneq entries.
* config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh_lane<mode>): Remove
AdvSIMD scalar modes.
(aarch64_sq<r>dmulh_laneq<mode>): New.
(aarch64_sq<r>dmulh_lane<mode>): New RTL pattern for Scalar AdvSIMD
modes.
* config/aarch64/arm_neon.h: Fix all the vq<r>dmulh_lane* intrinsics'
builtin implementations to relfect changes in RTL in aarch64-simd.md.
* config/aarch64/iterators.md (VCOND): New.
(VCONQ): New.
From-SVN: r195467
Diffstat (limited to 'gcc/tree-ssa-phiopt.c')
0 files changed, 0 insertions, 0 deletions