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| author | Bernd Schmidt <bernds@codesourcery.com> | 2010-07-02 16:25:59 +0000 |
|---|---|---|
| committer | Bernd Schmidt <bernds@gcc.gnu.org> | 2010-07-02 16:25:59 +0000 |
| commit | e4c6a07ab580140cc8780ff45a3b6e8f552d3df5 (patch) | |
| tree | 0b3ff1d243847f18cf8f9553e691d395447110b6 /gcc/tree-ssa-loop-prefetch.c | |
| parent | 18e8200f7082b15957ee05829ce51a06c381b378 (diff) | |
| download | gcc-e4c6a07ab580140cc8780ff45a3b6e8f552d3df5.zip gcc-e4c6a07ab580140cc8780ff45a3b6e8f552d3df5.tar.gz gcc-e4c6a07ab580140cc8780ff45a3b6e8f552d3df5.tar.bz2 | |
re PR tree-optimization/42172 (inefficient bit fields assignments)
PR target/42172
* config/arm/arm.c (thumb1_rtx_costs): Improve support for SIGN_EXTEND
and ZERO_EXTEND.
(arm_rtx_costs_1): Likewise.
(arm_size_rtx_costs): Use arm_rtx_costs_1 for these codes.
* config/arm/arm.md (is_arch6): New attribute.
(zero_extendhisi2, zero_extendqisi2, extendhisi2,
extendqisi2): Tighten the code somewhat, avoiding invalid
RTL to occur in the expander patterns.
(thumb1_zero_extendhisi2): Merge with thumb1_zero_extendhisi2_v6.
(thumb1_zero_extendhisi2_v6): Delete.
(thumb1_extendhisi2): Merge with thumb1_extendhisi2_v6.
(thumb1_extendhisi2_v6): Delete.
(thumb1_extendqisi2): Merge with thumb1_extendhisi2_v6.
(thumb1_extendqisi2_v6): Delete.
(zero_extendhisi2 for register input splitter): New.
(zero_extendqisi2 for register input splitter): New.
(thumb1_extendhisi2 for register input splitter): New.
(extendhisi2 for register input splitter): New.
(extendqisi2 for register input splitter): New.
(TARGET_THUMB1 extendqisi2 for memory input splitter): New.
(arm_zero_extendhisi2): Allow nonimmediate_operand for operand 1,
and add support for a register alternative requiring a split.
(thumb1_zero_extendqisi2): Likewise.
(arm_zero_extendqisi2): Likewise.
(arm_extendhisi2): Likewise.
(arm_extendqisi2): Likewise.
testsuite/
PR target/42172
* gcc.target/arm/pr42172-1.c: New test.
From-SVN: r161726
Diffstat (limited to 'gcc/tree-ssa-loop-prefetch.c')
0 files changed, 0 insertions, 0 deletions