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authorCarl Love <carll@us.ibm.com>2020-08-10 19:37:41 -0500
committerCarl Love <carll@us.ibm.com>2020-08-19 14:05:43 -0500
commit07d456bb80a16405723c98c2ab74ccc2a5a23898 (patch)
treee6c4c8e464473196b6eedf625cb1effe0480cefb /gcc/tree-ssa-loop-manip.c
parent95f17e26112d8a0700e8a9912e2f4f48a24ba1ea (diff)
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rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
gcc/ChangeLog 2020-08-19 Carl Love <cel@us.ibm.com> * config/rs6000/rs6000-builtin.def (BU_P10V_0, BU_P10V_1, BU_P10V_2, BU_P10V_3): Rename BU_P10V_VSX_0, BU_P10V_VSX_1, BU_P10V_VSX_2, BU_P10V_VSX_3 respectively. (BU_P10V_4): Remove. (BU_P10V_AV_0, BU_P10V_AV_1, BU_P10V_AV_2, BU_P10V_AV_3, BU_P10V_AV_4): New definitions for Power 10 Altivec macros. (VSTRIBR, VSTRIHR, VSTRIBL, VSTRIHL, VSTRIBR_P, VSTRIHR_P, VSTRIBL_P, VSTRIHL_P, MTVSRBM, MTVSRHM, MTVSRWM, MTVSRDM, MTVSRQM, VEXPANDMB, VEXPANDMH, VEXPANDMW, VEXPANDMD, VEXPANDMQ, VEXTRACTMB, VEXTRACTMH, VEXTRACTMW, VEXTRACTMD, VEXTRACTMQ): Replace macro expansion BU_P10V_1 with BU_P10V_AV_1. (VCLRLB, VCLRRB, VCFUGED, VCLZDM, VCTZDM, VPDEPD, VPEXTD, VGNB, VCNTMBB, VCNTMBH, VCNTMBW, VCNTMBD): Replace macro expansion BU_P10V_2 with BU_P10V_AV_2. (VEXTRACTBL, VEXTRACTHL, VEXTRACTWL, VEXTRACTDL, VEXTRACTBR, VEXTRACTHR, VEXTRACTWR, VEXTRACTDR, VINSERTGPRBL, VINSERTGPRHL, VINSERTGPRWL, VINSERTGPRDL, VINSERTVPRBL, VINSERTVPRHL, VINSERTVPRWL, VINSERTGPRBR, VINSERTGPRHR, VINSERTGPRWR, VINSERTGPRDR, VINSERTVPRBR, VINSERTVPRHR, VINSERTVPRWR, VREPLACE_ELT_V4SI, VREPLACE_ELT_UV4SI, VREPLACE_ELT_V2DF, VREPLACE_ELT_V4SF, VREPLACE_ELT_V2DI, VREPLACE_ELT_UV2DI, VREPLACE_UN_V4SI, VREPLACE_UN_UV4SI, VREPLACE_UN_V4SF, VREPLACE_UN_V2DI, VREPLACE_UN_UV2DI, VREPLACE_UN_V2DF, VSLDB_V16QI, VSLDB_V8HI, VSLDB_V4SI, VSLDB_V2DI, VSRDB_V16QI, VSRDB_V8HI, VSRDB_V4SI, VSRDB_V2DI): Replace macro expansion BU_P10V_3 with BU_P10V_AV_3. (VXXSPLTIW_V4SI, VXXSPLTIW_V4SF, VXXSPLTID): Replace macro expansion BU_P10V_1 with BU_P10V_AV_1. (XXGENPCVM_V16QI, XXGENPCVM_V8HI, XXGENPCVM_V4SI, XXGENPCVM_V2DI): Replace macro expansion BU_P10V_2 with BU_P10V_VSX_2. (VXXSPLTI32DX_V4SI, VXXSPLTI32DX_V4SF, VXXBLEND_V16QI, VXXBLEND_V8HI, VXXBLEND_V4SI, VXXBLEND_V2DI, VXXBLEND_V4SF, VXXBLEND_V2DF): Replace macor expansion BU_P10V_3 with BU_P10V_VSX_3. (XXEVAL, VXXPERMX): Replace macro expansion BU_P10V_4 with BU_P10V_VSX_4. (XVCVBF16SP, XVCVSPBF16): Replace macro expansion BU_VSX_1 with BU_P10V_VSX_1. Also change MISC to CONST. * config/rs6000/rs6000-c.c: (P10_BUILTIN_VXXPERMX): Replace with P10V_BUILTIN_VXXPERMX. (P10_BUILTIN_VCLRLB, P10_BUILTIN_VCLRLB, P10_BUILTIN_VCLRRB, P10_BUILTIN_VGNB, P10_BUILTIN_XXEVAL, P10_BUILTIN_VXXPERMX, P10_BUILTIN_VEXTRACTBL, P10_BUILTIN_VEXTRACTHL, P10_BUILTIN_VEXTRACTWL, P10_BUILTIN_VEXTRACTDL, P10_BUILTIN_VINSERTGPRHL, P10_BUILTIN_VINSERTGPRWL, P10_BUILTIN_VINSERTGPRDL, P10_BUILTIN_VINSERTVPRBL, P10_BUILTIN_VINSERTVPRHL, P10_BUILTIN_VEXTRACTBR, P10_BUILTIN_VEXTRACTHR, P10_BUILTIN_VEXTRACTWR, P10_BUILTIN_VEXTRACTDR, P10_BUILTIN_VINSERTGPRBR, P10_BUILTIN_VINSERTGPRHR, P10_BUILTIN_VINSERTGPRWR, P10_BUILTIN_VINSERTGPRDR, P10_BUILTIN_VINSERTVPRBR, P10_BUILTIN_VINSERTVPRHR, P10_BUILTIN_VINSERTVPRWR, P10_BUILTIN_VREPLACE_ELT_UV4SI, P10_BUILTIN_VREPLACE_ELT_V4SI, P10_BUILTIN_VREPLACE_ELT_UV2DI, P10_BUILTIN_VREPLACE_ELT_V2DI, P10_BUILTIN_VREPLACE_ELT_V2DF, P10_BUILTIN_VREPLACE_UN_UV4SI, P10_BUILTIN_VREPLACE_UN_V4SI, P10_BUILTIN_VREPLACE_UN_V4SF, P10_BUILTIN_VREPLACE_UN_UV2DI, P10_BUILTIN_VREPLACE_UN_V2DI, P10_BUILTIN_VREPLACE_UN_V2DF, P10_BUILTIN_VSLDB_V16QI, P10_BUILTIN_VSLDB_V16QI, P10_BUILTIN_VSLDB_V8HI, P10_BUILTIN_VSLDB_V4SI, P10_BUILTIN_VSLDB_V2DI, P10_BUILTIN_VXXSPLTIW_V4SI, P10_BUILTIN_VXXSPLTIW_V4SF, P10_BUILTIN_VXXSPLTID, P10_BUILTIN_VXXSPLTI32DX_V4SI, P10_BUILTIN_VXXSPLTI32DX_V4SF, P10_BUILTIN_VXXBLEND_V16QI, P10_BUILTIN_VXXBLEND_V8HI, P10_BUILTIN_VXXBLEND_V4SI, P10_BUILTIN_VXXBLEND_V2DI, P10_BUILTIN_VXXBLEND_V4SF, P10_BUILTIN_VXXBLEND_V2DF, P10_BUILTIN_VSRDB_V16QI, P10_BUILTIN_VSRDB_V8HI, P10_BUILTIN_VSRDB_V4SI, P10_BUILTIN_VSRDB_V2DI, P10_BUILTIN_VSTRIBL, P10_BUILTIN_VSTRIHL, P10_BUILTIN_VSTRIBL_P, P10_BUILTIN_VSTRIHL_P, P10_BUILTIN_VSTRIBR, P10_BUILTIN_VSTRIHR, P10_BUILTIN_VSTRIBR_P, P10_BUILTIN_VSTRIHR_P, P10_BUILTIN_MTVSRBM, P10_BUILTIN_MTVSRHM, P10_BUILTIN_MTVSRWM, P10_BUILTIN_MTVSRDM, P10_BUILTIN_MTVSRQM, P10_BUILTIN_VCNTMBB, P10_BUILTIN_VCNTMBH, P10_BUILTIN_VCNTMBW, P10_BUILTIN_VCNTMBD, P10_BUILTIN_VEXPANDMB, P10_BUILTIN_VEXPANDMH, P10_BUILTIN_VEXPANDMW, P10_BUILTIN_VEXPANDMD, P10_BUILTIN_VEXPANDMQ, P10_BUILTIN_VEXTRACTMB, P10_BUILTIN_VEXTRACTMH, P10_BUILTIN_VEXTRACTMW, P10_BUILTIN_VEXTRACTMD, P10_BUILTIN_VEXTRACTMQ, P10_BUILTIN_XVTLSBB_ZEROS, P10_BUILTIN_XVTLSBB_ONES): Replace with P10V_BUILTIN_VCLRLB, P10V_BUILTIN_VCLRLB, P10V_BUILTIN_VCLRRB, P10V_BUILTIN_VGNB, P10V_BUILTIN_XXEVAL, P10V_BUILTIN_VXXPERMX, P10V_BUILTIN_VEXTRACTBL, P10V_BUILTIN_VEXTRACTHL, P10V_BUILTIN_VEXTRACTWL, P10V_BUILTIN_VEXTRACTDL, P10V_BUILTIN_VINSERTGPRHL, P10V_BUILTIN_VINSERTGPRWL, P10V_BUILTIN_VINSERTGPRDL, P10V_BUILTIN_VINSERTVPRBL,P10V_BUILTIN_VINSERTVPRHL, P10V_BUILTIN_VEXTRACTBR, P10V_BUILTIN_VEXTRACTHR P10V_BUILTIN_VEXTRACTWR, P10V_BUILTIN_VEXTRACTDR, P10V_BUILTIN_VINSERTGPRBR, P10V_BUILTIN_VINSERTGPRHR, P10V_BUILTIN_VINSERTGPRWR, P10V_BUILTIN_VINSERTGPRDR, P10V_BUILTIN_VINSERTVPRBR, P10V_BUILTIN_VINSERTVPRHR, P10V_BUILTIN_VINSERTVPRWR, P10V_BUILTIN_VREPLACE_ELT_UV4SI, P10V_BUILTIN_VREPLACE_ELT_V4SI, P10V_BUILTIN_VREPLACE_ELT_UV2DI, P10V_BUILTIN_VREPLACE_ELT_V2DI, P10V_BUILTIN_VREPLACE_ELT_V2DF, P10V_BUILTIN_VREPLACE_UN_UV4SI, P10V_BUILTIN_VREPLACE_UN_V4SI, P10V_BUILTIN_VREPLACE_UN_V4SF, P10V_BUILTIN_VREPLACE_UN_UV2DI, P10V_BUILTIN_VREPLACE_UN_V2DI, P10V_BUILTIN_VREPLACE_UN_V2DF, P10V_BUILTIN_VSLDB_V16QI, P10V_BUILTIN_VSLDB_V16QI, P10V_BUILTIN_VSLDB_V8HI, P10V_BUILTIN_VSLDB_V4SI, P10V_BUILTIN_VSLDB_V2DI, P10V_BUILTIN_VXXSPLTIW_V4SI, P10V_BUILTIN_VXXSPLTIW_V4SF, P10V_BUILTIN_VXXSPLTID, P10V_BUILTIN_VXXSPLTI32DX_V4SI, P10V_BUILTIN_VXXSPLTI32DX_V4SF, P10V_BUILTIN_VXXBLEND_V16QI, P10V_BUILTIN_VXXBLEND_V8HI, P10V_BUILTIN_VXXBLEND_V4SI, P10V_BUILTIN_VXXBLEND_V2DI, P10V_BUILTIN_VXXBLEND_V4SF, P10V_BUILTIN_VXXBLEND_V2DF, P10V_BUILTIN_VSRDB_V16QI, P10V_BUILTIN_VSRDB_V8HI, P10V_BUILTIN_VSRDB_V4SI, P10V_BUILTIN_VSRDB_V2DI, P10V_BUILTIN_VSTRIBL, P10V_BUILTIN_VSTRIHL, P10V_BUILTIN_VSTRIBL_P, P10V_BUILTIN_VSTRIHL_P, P10V_BUILTIN_VSTRIBR, P10V_BUILTIN_VSTRIHR, P10V_BUILTIN_VSTRIBR_P, P10V_BUILTIN_VSTRIHR_P, P10V_BUILTIN_MTVSRBM, P10V_BUILTIN_MTVSRHM, P10V_BUILTIN_MTVSRWM, P10V_BUILTIN_MTVSRDM, P10V_BUILTIN_MTVSRQM, P10V_BUILTIN_VCNTMBB, P10V_BUILTIN_VCNTMBH, P10V_BUILTIN_VCNTMBW, P10V_BUILTIN_VCNTMBD, P10V_BUILTIN_VEXPANDMB, P10V_BUILTIN_VEXPANDMH, P10V_BUILTIN_VEXPANDMW, P10V_BUILTIN_VEXPANDMD, P10V_BUILTIN_VEXPANDMQ, P10V_BUILTIN_VEXTRACTMB, P10V_BUILTIN_VEXTRACTMH, P10V_BUILTIN_VEXTRACTMW, P10V_BUILTIN_VEXTRACTMD, P10V_BUILTIN_VEXTRACTMQ, P10V_BUILTIN_XVTLSBB_ZEROS, P10V_BUILTIN_XVTLSBB_ONES respectively. * config/rs6000/rs6000-call.c: Ditto above, change P10_BUILTIN_name to P10V_BUILTIN_name. (P10_BUILTIN_XVCVSPBF16, P10_BUILTIN_XVCVBF16SP): Change to P10V_BUILTIN_XVCVSPBF16, P10V_BUILTIN_XVCVBF16SP respectively.
Diffstat (limited to 'gcc/tree-ssa-loop-manip.c')
0 files changed, 0 insertions, 0 deletions