diff options
| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2016-11-03 23:32:07 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2016-11-03 23:32:07 +0000 |
| commit | f2834ebc00d847dcac85c44640a2c7fb2cdd340e (patch) | |
| tree | c9942ab81dd9456b420d9c144bde4c23c85ee2bf /gcc/tree-ssa-loop-im.c | |
| parent | 0bc36dec0f6a5d73b79e78c549533261b76602ec (diff) | |
| download | gcc-f2834ebc00d847dcac85c44640a2c7fb2cdd340e.zip gcc-f2834ebc00d847dcac85c44640a2c7fb2cdd340e.tar.gz gcc-f2834ebc00d847dcac85c44640a2c7fb2cdd340e.tar.bz2 | |
re PR target/78192 (extract from vector registers to int results in wrong data order)
2016-11-03 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/78192
* config/rs6000/vsx.md (vsx_extract_<mode>_di): The element number
has already been adjusted for endianness, so don't adjust it any
further.
From-SVN: r241834
Diffstat (limited to 'gcc/tree-ssa-loop-im.c')
0 files changed, 0 insertions, 0 deletions