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| author | Richard Sandiford <rsandifo@redhat.com> | 2004-08-23 07:59:27 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2004-08-23 07:59:27 +0000 |
| commit | 3d1f285d085b455b12954bc7162307ed1ae58925 (patch) | |
| tree | ba55effde3a479b22b09d5d780a402b43ce7c319 /gcc/tree-ssa-loop-im.c | |
| parent | c0e1b12feef416da65d62963b3dbff4c4ee2d903 (diff) | |
| download | gcc-3d1f285d085b455b12954bc7162307ed1ae58925.zip gcc-3d1f285d085b455b12954bc7162307ed1ae58925.tar.gz gcc-3d1f285d085b455b12954bc7162307ed1ae58925.tar.bz2 | |
mips.md (one_cmpl[sd]i2): Redefine using :GPR.
* config/mips/mips.md (one_cmpl[sd]i2): Redefine using :GPR.
(and[sd]3, ior[sd]i3, xor[sd]i3): Likewise. Change 32-bit patterns
to use register_operand rather than uns_arith_operand as the predicate
for operand 1. Remove redundant MIPS16 force_reg() for operand 1.
(*and[sd]i3, *ior[sd]i3, *xor[sd]i3): Name formerly unnamed patterns.
Redefine using :GPR. Make same predicate change here. Extend the
commutativity of operands 1 and 2 from the SImode version to the
DImode one.
(*and[sd]i3_mips16, *ior[sd]i3_mips16, *xor[sd]i3_mips16): Likewise,
but with no predicate changes.
(*nor[sd]i3): Redefine using :GPR.
From-SVN: r86413
Diffstat (limited to 'gcc/tree-ssa-loop-im.c')
0 files changed, 0 insertions, 0 deletions