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| author | Haochen Jiang <haochen.jiang@intel.com> | 2023-07-07 15:53:42 +0800 |
|---|---|---|
| committer | Haochen Jiang <haochen.jiang@intel.com> | 2023-07-12 13:08:42 +0800 |
| commit | d9f9e53e3a0ce4280bf612cd6f59afa26fe81419 (patch) | |
| tree | cdceba1316ee7bb182a366b4ad3f8c70b4414e47 /gcc/tree-ssa-loop-ch.cc | |
| parent | ce0583160810c3dbf1624686356de45089ea5d4f (diff) | |
| download | gcc-d9f9e53e3a0ce4280bf612cd6f59afa26fe81419.zip gcc-d9f9e53e3a0ce4280bf612cd6f59afa26fe81419.tar.gz gcc-d9f9e53e3a0ce4280bf612cd6f59afa26fe81419.tar.bz2 | |
i386: Guard 128 bit VAES builtins with AVX512VL
Since commit 24a8acc, 128 bit intrin is enabled for VAES. However,
AVX512VL is not checked until we reached into pattern, which reports an
ICE.
Added an AVX512VL guard at builtin to report error when checking ISA
flags.
gcc/ChangeLog:
* config/i386/i386-builtins.cc (ix86_init_mmx_sse_builtins):
Add OPTION_MASK_ISA_AVX512VL.
* config/i386/i386-expand.cc (ix86_check_builtin_isa_match):
Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx512vl-vaes-1.c: New test.
Diffstat (limited to 'gcc/tree-ssa-loop-ch.cc')
0 files changed, 0 insertions, 0 deletions