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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-03-15 10:45:11 +0100 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-07-12 16:05:50 +0800 |
| commit | d05c8b016fb96cdcc445406469867b757776894e (patch) | |
| tree | 1aab1ee7a3b34ba3b33e2c75e725815b1f1b8c12 /gcc/tree-ssa-loop-ch.cc | |
| parent | 13c556d6ae84be3ee2bc245a56eafa58221de86a (diff) | |
| download | gcc-d05c8b016fb96cdcc445406469867b757776894e.zip gcc-d05c8b016fb96cdcc445406469867b757776894e.tar.gz gcc-d05c8b016fb96cdcc445406469867b757776894e.tar.bz2 | |
riscv: xtheadbb: Add sign/zero extension support for th.ext and th.extu
The current support of the bitfield-extraction instructions
th.ext and th.extu (XTheadBb extension) only covers sign_extract
and zero_extract. This patch add support for sign_extend and
zero_extend to avoid any shifts for sign or zero extensions.
gcc/ChangeLog:
* config/riscv/riscv.md: No base-ISA extension splitter for XThead*.
* config/riscv/thead.md (*extend<SHORT:mode><SUPERQI:mode>2_th_ext):
New XThead extension INSN.
(*zero_extendsidi2_th_extu): New XThead extension INSN.
(*zero_extendhi<GPR:mode>2_th_extu): New XThead extension INSN.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadbb-ext-1.c: New test.
* gcc.target/riscv/xtheadbb-extu-1.c: New test.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'gcc/tree-ssa-loop-ch.cc')
0 files changed, 0 insertions, 0 deletions