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author | Roger Sayle <roger@nextmovesoftware.com> | 2023-07-12 14:09:54 +0100 |
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committer | Roger Sayle <roger@nextmovesoftware.com> | 2023-07-12 14:10:58 +0100 |
commit | 46ade8c9cc860170ab4253cffd24169efa46ca70 (patch) | |
tree | 745f0049d0ff3bf4148b00d13a8db44ea4551cc4 /gcc/tree-ssa-loop-ch.cc | |
parent | a454325bea77a0dd79415480d48233a7c296bc0a (diff) | |
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i386: Tweak ix86_expand_int_compare to use PTEST for vector equality.
I've come up with an alternate/complementary/supplementary fix to the
patch https://gcc.gnu.org/pipermail/gcc-patches/2023-June/622706.html
for generating the PTEST during RTL expansion, rather than rely on
this being caught/optimized later during STV.
You'll notice in this patch, the tests for TARGET_SSE4_1 and TImode
appear last. When I was writing this, I initially also added support
for AVX VPTEST and OImode, before realizing that x86 doesn't (yet)
support 256-bit OImode (which also explains why we don't have an OImode
to V1OImode scalar-to-vector pass). Retaining this clause ordering
should minimize the lines changed if things change in future.
2023-07-12 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/i386/i386-expand.cc (ix86_expand_int_compare): If
testing a TImode SUBREG of a 128-bit vector register against
zero, use a PTEST instruction instead of first moving it to
a pair of scalar registers.
Diffstat (limited to 'gcc/tree-ssa-loop-ch.cc')
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