aboutsummaryrefslogtreecommitdiff
path: root/gcc/tree-ssa-loop-ch.cc
diff options
context:
space:
mode:
authorChristoph Müllner <christoph.muellner@vrull.eu>2023-04-24 23:54:16 +0200
committerKito Cheng <kito.cheng@sifive.com>2023-07-12 16:12:28 +0800
commit423604278ed550f07f80c9687a441c58a6cd6e85 (patch)
tree262a7869e76d9f01f006466587aa0d2aaee3ac2c /gcc/tree-ssa-loop-ch.cc
parent96ad6ab29b3d6d8646c97760cc87a17f405e09d2 (diff)
downloadgcc-423604278ed550f07f80c9687a441c58a6cd6e85.zip
gcc-423604278ed550f07f80c9687a441c58a6cd6e85.tar.gz
gcc-423604278ed550f07f80c9687a441c58a6cd6e85.tar.bz2
riscv: Prepare backend for index registers
RISC-V does currently not support index registers. However, there are some vendor extensions that specify them. Let's do the necessary changes in the backend so that we can add support for such a vendor extension in the future. This is a non-functional change without any intended side-effects. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_regno_ok_for_index_p): New prototype. (riscv_index_reg_class): Likewise. * config/riscv/riscv.cc (riscv_regno_ok_for_index_p): New function. (riscv_index_reg_class): New function. * config/riscv/riscv.h (INDEX_REG_CLASS): Call new function riscv_index_reg_class(). (REGNO_OK_FOR_INDEX_P): Call new function riscv_regno_ok_for_index_p(). Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'gcc/tree-ssa-loop-ch.cc')
0 files changed, 0 insertions, 0 deletions