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| author | Andrew Stubbs <ams@codesourcery.com> | 2020-02-21 11:07:55 +0000 |
|---|---|---|
| committer | Andrew Stubbs <ams@codesourcery.com> | 2020-02-21 11:56:20 +0000 |
| commit | 3abfd4f3410af27060a11b8adaa9836d5a77eae1 (patch) | |
| tree | 8207446cffd4c3ec2a2b8b6ea7eaadeb72e5ebc6 /gcc/tree-ssa-alias.c | |
| parent | 2291d1fd85744f26bf4943187266d28c3b89d200 (diff) | |
| download | gcc-3abfd4f3410af27060a11b8adaa9836d5a77eae1.zip gcc-3abfd4f3410af27060a11b8adaa9836d5a77eae1.tar.gz gcc-3abfd4f3410af27060a11b8adaa9836d5a77eae1.tar.bz2 | |
amdgcn: Align VGPR pairs
Aligning the registers is not needed by the architecture, but doing so
allows us to remove the requirement for bug-prone early-clobber
constraints from many split patterns (and avoid adding more in future).
2020-02-21 Andrew Stubbs <ams@codesourcery.com>
gcc/
* config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align VGPR pairs.
* config/gcn/gcn-valu.md (addv64di3): Remove early-clobber.
(addv64di3_exec): Likewise.
(subv64di3): Likewise.
(subv64di3_exec): Likewise.
(addv64di3_zext): Likewise.
(addv64di3_zext_exec): Likewise.
(addv64di3_zext_dup): Likewise.
(addv64di3_zext_dup_exec): Likewise.
(addv64di3_zext_dup2): Likewise.
(addv64di3_zext_dup2_exec): Likewise.
(addv64di3_sext_dup2): Likewise.
(addv64di3_sext_dup2_exec): Likewise.
(<expander>v64di3): Likewise.
(<expander>v64di3_exec): Likewise.
(*<reduc_op>_dpp_shr_v64di): Likewise.
(*plus_carry_dpp_shr_v64di): Likewise.
* config/gcn/gcn.md (adddi3): Likewise.
(addptrdi3): Likewise.
(<expander>di3): Likewise.
Diffstat (limited to 'gcc/tree-ssa-alias.c')
0 files changed, 0 insertions, 0 deletions