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| author | Kito Cheng <kito.cheng@sifive.com> | 2020-02-18 13:47:50 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2020-02-19 13:03:51 +0800 |
| commit | bfe78b08471fa6daffb8e8e8e70bd5b1d3071ff6 (patch) | |
| tree | 08b3bf5f5cc03b417b6ffc596ba93c0173404012 /gcc/tree-sra.c | |
| parent | 242b4fb7f4e6c6224e727fa5e9ed8a776d16ccf9 (diff) | |
| download | gcc-bfe78b08471fa6daffb8e8e8e70bd5b1d3071ff6.zip gcc-bfe78b08471fa6daffb8e8e8e70bd5b1d3071ff6.tar.gz gcc-bfe78b08471fa6daffb8e8e8e70bd5b1d3071ff6.tar.bz2 | |
RISC-V: Using fmv.x.w/fmv.w.x rather than fmv.x.s/fmv.s.x
- fmv.x.s/fmv.s.x renamed to fmv.x.w/fmv.w.x in the latest RISC-V ISA
manual.
- Tested rv32gc/rv64gc on bare-metal with qemu.
ChangeLog
gcc/
Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x
rather than fmv.x.s/fmv.s.x.
Diffstat (limited to 'gcc/tree-sra.c')
0 files changed, 0 insertions, 0 deletions