RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit

Previously,  I add TARGET_64BIT condtion to block VLS modes with size = 64bit in RV32 system
E.g. V8QI

Since I realized such modes may cause inferior codegen for some situations in RV32 system.

However, this is really quite ugly and it cause ICE for some cases in RV32:

FAIL: gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c (internal compiler error: in require, at machmode.h:313)
3937FAIL: gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c (test for excess errors)

For inferior codegen in RV32 system, we should try another reasonable approach to fix it.

Remove those TARGET_64BIT and fix ICE.

gcc/ChangeLog:

	* config/riscv/riscv-vector-switch.def (VLS_ENTRY): Remove TARGET_64BIT

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve64d-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve64f-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve64x-1.c: Ditto.

0 files changed, 0 insertions, 0 deletions