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| author | Kito Cheng <kito.cheng@sifive.com> | 2023-12-04 14:17:52 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-12-04 14:38:10 +0800 |
| commit | ba94969bad24d57895b02cc2d4663462f8fb5bc5 (patch) | |
| tree | edb660dfc7c9cd5017933984592ac68c0b93c546 /gcc/tree-pass.h | |
| parent | 9e12010b5e724277ea44c300630802f464407d8d (diff) | |
| download | gcc-ba94969bad24d57895b02cc2d4663462f8fb5bc5.zip gcc-ba94969bad24d57895b02cc2d4663462f8fb5bc5.tar.gz gcc-ba94969bad24d57895b02cc2d4663462f8fb5bc5.tar.bz2 | |
RISC-V: Add sifive-x280 to -mcpu
x280 is one of SiFive core, and it release for a while, also
upstream LLVM already support that.
[1] https://www.sifive.com/cores/intelligence-x280
gcc/ChangeLog:
* config/riscv/riscv-cores.def: Add sifive-x280.
* doc/invoke.texi (RISC-V Options): Add sifive-x280
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-sifive-x280.c: New test.
Diffstat (limited to 'gcc/tree-pass.h')
0 files changed, 0 insertions, 0 deletions