RISC-V: Fix splitter for 32-bit AND on 64-bit target.

Fixes github.com/riscv/riscv-gcc issue #161.  We were accidentally using
BITS_PER_WORD to compute shift counts when we should have been using the
bitsize of the operand modes.  This was wrong when we had an SImode shift
and a 64-bit target.

	Andrew Waterman  <andrew@sifive.com>
	gcc/
	* config/riscv/riscv.md (lshrsi3_zero_extend_3+1): Use operands[1]
	bitsize	instead of BITS_PER_WORD.
	gcc/testsuite/
	* gcc.target/riscv/shift-shift-2.c: Add one more test.

From-SVN: r273230

0 files changed, 0 insertions, 0 deletions