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authorKewen Lin <linkw@linux.ibm.com>2023-04-26 00:21:14 -0500
committerKewen Lin <linkw@linux.ibm.com>2023-04-26 00:21:14 -0500
commit33a44e3aa81f9fdf8f6b87018abd4c664e545b53 (patch)
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parentfd75f6ae5625f087980ff4a7e76cc6284cfe5a3e (diff)
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rs6000: Guard power9-vector for vsx_scalar_cmp_exp_qp_* [PR108758]
__builtin_vsx_scalar_cmp_exp_qp_{eq,gt,lt,unordered} used to be guarded with condition TARGET_P9_VECTOR before new bif framework was introduced (r12-5752-gd08236359eb229), since r12-5752 they are placed under stanza ieee128-hw, that is to check condition TARGET_FLOAT128_HW, it caused test case float128-cmp2-runnable.c to fail at -m32 as the condition TARGET_FLOAT128_HW isn't satisified with -m32. By checking the commit history, I didn't see any notes on why this condition change on them was made, so this patch is to move these bifs from stanza ieee128-hw to stanza power9-vector as before. PR target/108758 gcc/ChangeLog: * config/rs6000/rs6000-builtins.def (__builtin_vsx_scalar_cmp_exp_qp_eq, __builtin_vsx_scalar_cmp_exp_qp_gt __builtin_vsx_scalar_cmp_exp_qp_lt, __builtin_vsx_scalar_cmp_exp_qp_unordered): Move from stanza ieee128-hw to power9-vector.
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